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M25P10
1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface
PRELIMINARY DATA
s s s s s s s s s s s s s
1 Mbit PAGED Flash Memory 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL 256 Kbit SECTOR ERASE IN 1 s TYPICAL BULK ERASE IN 2 s TYPICAL SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 20 MHz CLOCK RATE AVAILABLE SUPPORTS POSITIVE CLOCK SPI MODES DEEP POWER DOWN MODE (1 A TYPICAL) ELECTRONIC SIGNATURE 10,000 ERASE/PROG CYCLES PER SECTOR 20 YEARS DATA RETENTION -40 TO 85C TEMPERATURE RANGE
8 1
SO8 (MN) 150 mil width
8 1
SO8 (MW) 200 mil width
DESCRIPTION The M25P10 is an 1 Mbit Paged Flash Memory fabricated with STMicroelectronics High Endurance CMOS technology. The memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q). The device connected to the bus is selected when the chip select input (S) goes low. Data is clocked in during the low to high transition of clock C, data
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select
D C S W HOLD M25P10
Q
S
W HOLD VCC VSS
Write Protect Hold Supply Voltage Ground
VSS
AI03744
June 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M25P10
Figure 2. SO Connections Chip Select (S) When S is high, the memory is deselected and the Q output pin is at high impedance and, unless an internal Read, Program, Erase or Write Status Register operation is underway, the device will be in the Standby Power mode (this is not the Deep Power Down mode). S low enables the memory, placing it in the active power mode. It should be noted that after power-on, a high to low transition on S is required prior to the start of any operation. Hold (HOLD) The HOLD pin is used to pause serial communications with a SPI memory without resetting the serial sequence. To take the Hold condition into account, the product must be selected. The HOLD condition is validated by a 0 state on the Hold pin synchronized with the 0 state on the Clock, as shown in Figure 4. The DeHOLD condition is validated by a 1 state on the Hold pin synchronized with the 0 state on the Clock. During the Hold condition D, Q, and C are at a high impedance state. When the memory is under HOLD condition, it is possible to deselect the device. Then, the protocol is reset. The memory remains on HOLD as long as the Hold pin is Low. To restart communication with the device, it is necessary to both DeHOLD (H = 1) and to SELECT the memory. Write Protect (W) This pin is for hardware write protection of the Status Register (SR); except WIP and WEL bits. When bit 7 (SRWD) of the status register is 0 (the initial delivery state); it is possible to write the SR once the WEL (Write Enable Latch) has been set with the WREN instruction and whatever is the status of pin W (high or low).
M25P10 S Q W VSS 1 2 3 4 8 7 6 5
AI03745
VCC HOLD C D
is clocked out during the high to low transition of clock C SIGNALS DESCRIPTION Serial Output (Q) The output pin is used to transfer data serially out of the memory. Data is shifted out on the falling edge of the serial clock. Serial Input (D) The input pin is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Input is latched on the rising edge of the serial clock. Serial Clock (C) The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input.
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering SO8: 40 seconds Value -40 to 85 -65 to 150 215 -0.3 to 5.0 -0.6 to 5.0 2000 Unit C C C V V V
Input and Output Voltage Range (with respect to Ground) Supply Voltage Range Electrostatic Discharge Voltage (Human Body model) 2
Note: 1. Except for the rating "Ambient Operating Temperature Range", stresses above those listed in this table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
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Figure 3. Microcontroller and Memory Devices on the SPI Bus
SPI Interface with SDO (CPOL, CPHA) = SDI ('0', '0') or ('1', '1') SCK Master (ST6, ST7, ST9, ST10, Others)
CQD M25P10
CQD M25P10 S
CQD M25P10 S
CS3
CS2
CS1
S
AI03746
Once bit 7 (SRWD) of the status register has been set to 1, the possibility to rewrite the SR depends on the logical level present at pin W: - If W pin is high, it will be possible to rewrite the status register after having set the WEL (Write Enable Latch). - If W pin is low, any attempt to modify the status register will be ignored by the device even if the WEL was set. As a consequence: all the data bytes in the memory area software protected (SPM) by the BPi bits of the status register are also hardware protected against data modification and can be seen as a Read Only memory area. This mode is called the Hardware Protected Mode (HPM).
It is possible to enter the Hardware Protected Mode (HPM) by setting SRWD bit after pulling down the W pin or by pulling down the W pin after setting SRWD bit. The only way to abort the Hardware Protected Mode once entered is to pull high the W pin. If W pin is permanently tied to high level, the Hardware Protected Mode will never be activated and the memory will only allow the user to software protect a part of the memory with the BPi bits of the status register. All protection features of the device are summarized in Table 3.
Figure 4. Hold Condition Activation
CLOCK
HOLD PIN
MEMORY STATUS
ACTIVE
HOLD
ACTIVE
HOLD
ACTIVE
AI02029B
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Figure 5. M25P10-Compatible SPI Modes
CPOL CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
Clock Polarity (CPOL) and Clock Phase (CPHA) with SPI Bus As shown in Figure 5, the M25P10 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: (CPOL, CPHA) = ('0', '0') or (CPOL, CPHA) = ('1', '1'). For these two modes, input data is latched in by the low to high transition of clock C, and output data is available from the high to low transition of Clock (C).The difference between (CPOL, CPHA) = (0, 0) and (CPOL, CPHA) = (1, 1) is the clock polarity when in stand-by: C remains at '0' for (CPOL, CPHA) = (0, 0) and C remains at '1' for (CPOL, CPHA) = (1, 1) when there is no data transfer. MEMORY ORGANIZATION The memory is organized in 131,072 words of 8 bits each. The device features 1,024 pages of 128 bytes each. Each page can be individually programmed (bits are programmed from `1' to '0' state).
The device is also organized in 4 sectors of 262,144 bits (32,768 x 8 bits) each.The device is Sector or Bulk Erasable but not Page Erasable (bits are erased from '0' to '1' state). OPERATIONS All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any Table 4. Memory Organization
Sector 3 2 1 0 Address Range 18000h 10000h 08000h 00000h 1FFFFh 17FFFh 0FFFFh 07FFFh
Table 3. Protection Features
W X 1 SRWD 0 1 Status Register (SR) Writeable after setting WEL Writeable after setting WEL Data Bytes (Software Protected Area by BPi bits) Software protected by the BPi bits of the Status Register Software protected by the BPi bits of the Status Register Hardware protected by the BPi bits of the Status Register and the W pin Mode SPM SPM Data Bytes (Unprotected Area) Paged Programmable and Sector Erasable Paged Programmable and Sector Erasable Paged Programmable and Sector Erasable
0
Note: 1. 2. 3. 4. 5. 6. 7.
1
Hardware protected
HPM
SPM: Software Protected Mode. HPM: Hardware Protected Mode. BPi: Bits BP0 and BP1 of the Status Register. WEL: Write Enable Latch of the Status Register. W: Write Protect Input Pin. SRWD: Status Register Write Disable Bits of the Status Register. The device is Bulk Erasable if, and only if, (BP0, BP1) = (0, 0), (see Bulk Erase paragraph).
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Figure 6. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Size of the Read only Memory area
1FF80h
1FFFFh
Y Decoder
An
An + 7Fh
128 Bytes
0000h
007Fh
X Decoder
AI03747
Table 5. Protected Area Sizes
BP1 0 0 1 1 BP0 0 1 0 1 Software Protected Area none Upper quarter = Sector 3 Upper half = Sectors 2 & 3 Whole memory= Sectors 0, 1, 2 & 3
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Table 6. Instruction Set
Instruc tion WREN WRDI RDSR WRSR READ PP SE BE DP RES Description Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Program up to 128 Data bytes to Memory Array Sector Erase (set to FFh) one sector of Memory Array Bulk Erase (set to FFh) whole of Memory Array Enter Deep Power-down mode Release from Deep Powerdown mode, and Read Electronic Signature Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 1101 1000 1100 0111 1011 1001 1010 1011
operation, a one-byte instruction code must be sent to the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the device must have been previously selected (S = low). Table 6 shows the available instruction set. At Power-up and Power-down, the device must not be selected (that is the S input must follow the voltage applied on the VCC pin) until the supply voltage reaches the correct VCC values which are VCC(min) at Power-up and VSS at Power-down (a simple pull-up resistor on S insures safe and proper power up and down phases).
Read Data Byte(s) (READ) The device is first selected by putting S low. The Read instruction byte is followed by a three bytes address (A23-A0), each bit being latched-in during the rising edge of the clock (C). Then the data stored in the memory at the selected byte address is shifted out on the Q output pin, each bit being shifted out during the falling edge of the clock (C). The first byte addressed can be any byte within a page. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can therefore be read with a single Read instruction. When the highest address is reached, the address counter rolls over to 000000h allowing the read cycle to be continued indefinitely. The Read operation is terminated by deselecting the chip. The chip can be deselected at any time during data output. Any read attempt during an Erase, Program or Write Status Register cycle will be rejected and will deselect the chip without having any effects on the ongoing operation. The timing sequence is shown in Figure 11. Page Program (PP) Prior to any Page Program attempt, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows the execution of any further Page Program instruction. The Page Program instruction is entered by driving the Chip select input (S) low, followed by the instruction byte, 3 address bytes and at least 1 data byte on Data In input (D). If the least significant address bits differ from [A6A0]=000.0000, all transmitted data exceeding the addressed page boundary will roll over and will be programmed from address [A6-A0]=000.0000 of this same page. The Chip Select input (S) must be driven low for the entire duration of the sequence.
Figure 7. WREN: Set Write Enable Latch Sequence
S 0 C INSTRUCTION D HIGH IMPEDANCE Q
AI02281B
1
2
3
4
5
6
7
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M25P10
Figure 8. WRDI: Reset Write Enable Latch Sequence
S 0 C INSTRUCTION D HIGH IMPEDANCE Q
AI03750
1
2
3
4
5
6
7
If more than 128 bytes are sent to the device, previously latched data are discarded and the last 128 data bytes are guaranteed to be programmed correctly within the same page. If less than 128 Data bytes are sent to device; they are correctly programmed at the requested addresses without having any effects on the other bytes of the same Page. The device must be deselected just after the eighth bit of the last data byte has been latched in. If not, the Page Program instruction is not executed. As soon as the device is deselected, the self-timed Page Program cycle (tPP) is initiated. While the Page Program cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed Page Program cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. A Page Program instruction applied to a Page which is software protected by the BPi bits (see Table 4 and Table 5) is not initiated.
The timing sequence is shown in Figure 12. Write Enable (WREN) and Write Disable (WRDI) The Write Enable Latch must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) operation. The WREN instruction, whose timing sequence is shown in Figure 7, will set the latch and the WRDI instruction, whose timing sequence is shown in Figure 8, will reset the latch. The Write Enable Latch is reset under the following conditions: - Power on - WRDI instruction completion - WRSR instruction completion - Page Program instruction completion - Sector Erase instruction completion - Bulk Erase instruction completion. After completion of either WREN or WRDI instruction, the chip enters a wait state and waits for a deselect.
Figure 9. RDSR: Read Status Register Sequence
S 0 C INSTRUCTION D STATUS REG. OUT HIGH IMPEDANCE Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
STATUS REG. OUT
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Figure 10. WRSR: Write Status Register Sequence
S 0 C INSTRUCTION STATUS REG. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D HIGH IMPEDANCE Q
7 MSB
6
5
4
3
2
1
0
AI02282
Read Status Register (RDSR) The RDSR instruction provides access to the Status Register content. The Status Register may be read at any time, even during a Page Program, Sector Erase, Bulk Erase or Write Status Register. When one of these instructions is in progress, it is recommended to check the WIP bit before sending a new instruction to the device. For this, it is possible to continuously read the Status Register value. WIP bit: The Write-In-Process (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase operation. When set to a '1', such an operation is in progress, when set to a '0' no such operation is in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to a '1' the latch is set, when set to a '0' the latch is reset and no Write Status Register, Program or Erase sequence will be allowed. BP1,BP0 bits: The Block Protect bits BPi are nonvolatile bits. They define the size of the area to be software protected against Program and Erase operations. These bits are written with the WRSR instruction (see Table 5). Once (BP0, BP1) are set to a value different from (0,0), the relevant area becomes protected against Page Program and Sector Erase operations. BPi bits can be written provided that the Hardware Protected Mode has not been set. The Bulk Erase instruction is
Figure 11. READ: Read Data Bytes Sequence
S 0 C INSTRUCTION 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
D HIGH IMPEDANCE Q
23 22 21
3
2
1
0 DATA OUT 7 MSB
AI03748
6
5
4
3
2
1
0
Note: 1. Address bits A23 to A17 are Don't Care on the M25P10 series.
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Table 7. Status Register Format
b7 SRWD 0 0 0 BP1 BP0 WEL b0 WIP
Note: 1. SRWD, BP0 and BP1 are non-volatile read and write bits. 2. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device).
internally taken into account if, and only if, (BP0, BP1) = (0,0). SRWD bit: The SRWD bit operates together with the W pin. SRWD bit and W pin allow the part to be put in the Hardware protected mode. In this mode (W pin = 0 and SRWD = 1), the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read only bits and the Write Status Register (WRSR) instruction has no more effect on the device (please see the section entitled "Write Protect (W)" on page 2, and Table 3). Write in the Status Register (WRSR) Prior to any WRSR instruction, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows
the execution of any further WRSR instruction. The WRSR instruction is entered by driving the Chip select input (S) low, followed by the instruction byte and the data byte on Data In input (D). WRSR instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read at '0'. The device must be deselected just after the eighth bit of the data byte has been latched in. If not, the WRSR instruction is not executed. As soon as the device is deselected, the self-timed Write Status Register cycle (tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the WIP bit value. WIP is high during the self-timed Write Status Register cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The WRSR instruction allows the user to define the size of the software Protected area (Read Only) when setting the BP1,BP0 values, according to Table 4. The WRSR instruction also allows the user to set or reset the SRWD bit in accordance with the W pin. SRWD bit and W pin allow the part to be put in the Hardware protected mode (please see the sections entitled "Read Status Register (RDSR)" on page 8, "Write Protect (W)" on page 2, and Table 3). WRSR instruction has no effect on
Figure 12. PP: Page Program Sequence
S 0 C INSTRUCTION 24 BIT ADDRESS DATA BYTE 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
S 1050 1049 1052 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C DATA BYTE 2 DATA BYTE 3 DATA BYTE 128 1051 1053 2 1054 1 1055 0
AI03749
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
Note: 1. Address bits A23 to A17 are Don't Care on the M25P10 series.
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Figure 13. SE: Sector Erase Sequence
S 0 C INSTRUCTION 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751
Note: 1. Address bits A23 to A17 are Don't Care on the M25P10 series.
the device once the Hardware Protected Mode is entered. The timing sequence is shown in Figure 10. Sector Erase (SE) Prior to any Sector Erase attempt, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows the execution of any further Sector Erase. The Sector Erase instruction is entered by driving the Chip select input (S) low, followed by the instruction byte and 3 address bytes on Data In input (D). Any address of the Sector (see Table 4) is a valid address for the Sector Erase instruction. The Chip Select input (S) must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the
last address byte has been latched in. If not, the Sector Erase instruction is not executed. As soon as the device is deselected, the self-timed Sector Erase cycle (tSE) is initiated. While the Sector Erase cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed Sector Erase cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. A Sector Erase instruction applied to a Sector which is software protected by the BPi bits (see Table 4 and Table 5) is not initiated. The timing sequence is shown in Figure 13. Bulk Erase (BE) Prior to any Bulk Erase attempt, a write enable instruction (WREN) must have been previously sent (the S input driven low, WREN instruction properly transmitted and the S input driven high). After the WREN instruction decoding, the memory
Figure 14. BE: Bulk Erase Sequence
S 0 C INSTRUCTION D 1 2 3 4 5 6 7
AI03752
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Figure 15. DP: Enter Deep Power Down Mode Sequence
S 0 C INSTRUCTION D 1 2 3 4 5 6 7 tDP
Stand-by Power Down Mode
Deep Power Down Mode
AI03753
sets the Write Enable Latch (WEL) which allows the execution of any further Bulk Erase. The Bulk Erase instruction is entered by driving the Chip select input (S) low, followed by the instruction byte on Data In input (D). The Chip Select input (S) must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the instruction byte has been latched in. If not, the Bulk Erase instruction is not executed. As soon as the device is deselected, the self-timed Bulk Erase cycle (t BE) is initiated. While the Bulk Erase cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed Bulk Erase cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The Bulk Erase instruction is internally taken into account if, and only if, (BP0, BP1) = (0,0). In other
words, the Bulk Erase instruction is ignored if at least one Sector is software protected. In this case the Bulk Erase instruction is discarded and none of the Sectors are erased. The timing sequence is shown in Figure 14. Enter Deep Power Down Mode (DP) After Power-on, when S is high, the memory is deselected, the Q output pin is at high impedance and the device is in the Standby Power Mode state (ICC1). Under this state, the Memory waits for a select condition and is able to receive, decode and execute all instructions.This mode is not the Deep Power Down Mode which is entered by the way of a specific instruction. The purpose of the Deep Power down mode is to drastically reduce the standby current from ICC1 to ICC2 (see Table 10). Once the device has entered the Deep Power Down Mode, all instructions are ignored except the RES instruction which releases the part from this
Figure 16. RES: Release from Deep Power Down Mode and Read Electronic Signature Sequence
S 0 C INSTRUCTION 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
D HIGH IMPEDANCE Q
23 22 21
3
2
1
0 DATA OUT (Electronic Signature) 7 MSB Deep Power Down Mode Stand-by Power Down Mode
AI03755
6
5
4
3
2
1
0
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Figure 17. RES: Release from Deep Power Down Mode Sequence
S 0 C INSTRUCTION D 1 2 3 4 5 6 7 tRES
HIGH IMPEDANCE Q Deep Power Down Mode Stand-by Power Down Mode
AI03754
mode. At the same time, the RES instruction provides the Electronic Signature of the device on the Q output pin. At power down, the Deep Down Mode is automatically discarded. This causes the device to always wake up in the Standby Power Mode state after power-on. The DP instruction is entered by driving the Chip select input (S) low, followed by the instruction byte on Data In input (D). The Chip Select input (S) must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the instruction byte has been latched in. If not, the DP instruction is not executed. As soon as the device is deselected, it requires t DP to enter the Deep Power Down Mode where standby current is reduced to ICC2. The timing sequence is shown in Figure 15. Release from Deep Power Down Mode and Read Electronic Signature (RES) Once the device has entered the Deep Power Down Mode, all instructions are ignored except the RES instruction which releases the part from this mode. At the same time, the RES instruction provides the Electronic Signature of the device on the Q output pin. Except during an Erase, Program cycle or Write Status register, the RES instruction always provides access to the Electronic Signature of the device and can be applied even if the Deep Power Down Mode has not been entered. Any RES attempt during an Erase, Program cycle or Write Status register, will be rejected and will deselect the chip without having any effects on the ongoing Erase, Program cycle or Write Status Register.
The device is first selected by putting S low. The RES instruction byte is followed by a dummy three bytes address (A23-A0), each bit being latched-in on Data In input (D) during the rising edge of the clock (C). Then, the Electronic Signature stored in the memory is shifted out on the Q output pin, each bit being shifted out during the falling edge of the clock (C). It is possible to continuously read the Electronic Signature value. The RES operation is terminated by deselecting the chip after the Electronic Signature has been read at least one time (see Figure 16). At this step, the device is immediately put again in the Standby Power Mode state. It waits for a select condition and is able to receive, decode and execute all instructions. Deselecting the device after the 8 bits RES instruction has been sent but before the LSB of the Electronic Signature has been read, will insure the Deep Power Down Mode to be released but will generate a delay (tRES) before the device is put in Standby Power Mode state (see Figure 17) and S must remain high for at least tRES max value (see Table 13). POWER ON STATE At Power-up, the device must not be selected (that is the S input must follow the voltage supplied on the V CC pin) until the supply voltage reaches the minimum VCC value (2.7 V). Once VCC has reached the minimum operating voltage (2.7 V), the Chip Select input pin (S) must remain high for a time higher than tVSL min (See Table 8). After a Power up, the memory is in the following state:
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Table 8. Power-Up Timing and VWI Threshold (TA = -40 to 85 C)
Symbol IVSL 1 IPUW1 VWI1 Parameter VCC(min) to S low Time delay to Write operation Write Inhibit Voltage 1.5 Test Condition Min. 10 15 2.5 Max. Unit s ms V
Note: 1. These parameters are characterized only.
- The device is in the low power standby state (not the Deep Power Down Mode). - The chip is deselected. - The Write Enable Latch is reset. POWER UP OPERATION In order to prevent data corruption and inadvertent Page Program, Erase or Write Status Register operations, an internal VCC comparator inhibits all these features if the VCC voltage is lower than VWI (see Table 8). Once the voltage applied on the VCC pin goes over the V WI threshold (VCC>V WI): - Page Program, Erase and Write Status Register operations are allowed after a time-out of tPUW, as specified in Table 8. - This time-out delay allows the voltage applied on VCC pin to reach V CC(min) of the device. It should be noted that none of the device's operation are guaranteed till VCC is not VCC(min). DATA PROTECTION AND PROTOCOL CONTROL Once all bits of a Page Program, Sector Erase, Bulk Erase or Status Register Write instruction are received; the S input must be driven high (Deselect) right after the proper clock count in order to execute the instruction, that is the Chip Select S must driven high after a clock pulses count multiple of 8 bit. Attempting to access the memory array during a Write, Program or Erase cycle is ignored, however the internal cycle continues. ELECTRONIC SIGNATURE The device features an 8 bits Electronic Signature (10h) which can be read with the help of the RES instruction (please see the section entitled "Release from Deep Power Down Mode and Read Electronic Signature (RES)" on page 12). INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set at '1' (each byte = FFh). The
Table 9. Initial Status Register Format
b7 0 0 0 0 0 0 0 b0 0
Status Register content is 00h (all Status Register bits are '0').
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Table 10. DC Characteristics (TA = -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Stand-by mode Current Deep Power Down Current Operating Current (READ) Operating Current (PP) Operating Current (WRSR) Operating Current (SE) Operating Current (BE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -100 A VCC-0.2 S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 20 MHz, Q = open S = VCC S = VCC S = VCC S = VCC - 0.6 0.7VCC Test Condition Min. Max. 2 2 50 5 3 15 15 15 15 0.3VCC VCC+1 0.4 Unit A A A A mA mA mA mA mA V V V V
Table 11. Input Parameters 1 (TA = 25 C, f = 20 MHz)
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition Min. Max. 8 6 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 12. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Output Load 5 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC CL = 30 pF
Figure 18. AC Testing Input Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
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M25P10
Table 13. AC Characteristics
M25P10 Symbol Alt. Parameter VCC=2.7 to 3.6 V TA=-40 to 85C Min fC tSLCH tCHSL tCH 1 tCL 1 tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ 2 tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX 2 tHLQZ 2 tDP 2 tRES 2 tW tPP tSE tBE tLZ tHZ tCSH tDIS tV tHO tCLH tCLL tDSU tDH fC tCSS Clock Frequency S Active Setup Time (relative to C) S Not Active Hold Time (relative to C) Clock High Time Clock Low Time Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C) S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD to Output Low-Z HOLD to Output High-Z S High to Deep Power Down Mode S High to Stand-by Power Mode Write Status Register Cycle Time Page Program Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time 0 10 10 10 10 20 20 1.6 1.6 5 5 2 4 D.C. 10 10 22 22 5 5 10 10 50 20 20 Max 20 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ms s s Unit
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production. These parameters are specified with an output load capacitance of 30 pF.
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M25P10
Figure 19. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
HIGH IMPEDANCE
AI01447
Figure 20. Hold Timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
Figure 21. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCL
tSHQZ
LSB OUT
AI01449B
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M25P10
Table 14. Ordering Information Scheme
Example: M25P10 - V MW 6 T
Memory Capacity 10 1 Mbit (128K x 8) T
Option Tape and Reel Packing
Temperature Range 6 -40 C to 85 C
Operating Voltage V 2.7 V to 3.6 V MN MW
Package SO8 (150 mil width) SO8 (200 mil width)
ORDERING INFORMATION The notation used for the device number is as shown in Table 14. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office .
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M25P10
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 22. SO8 narrow (MN)
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Drawing is not to scale.
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M25P10
Table 16. SO8 - 8 lead Plastic Small Outline, 200 mils body width
mm Symb. Typ. A A1 A2 B C D E e H L N CP 1.27 0.20 0.35 - 5.15 5.20 - 7.70 0.50 0 8 0.10 0.10 Min. Max. 2.03 0.25 1.78 0.45 - 5.35 5.40 - 8.10 0.80 10 0.050 0.008 0.014 - 0.203 0.205 - 0.303 0.020 0 8 0.004 0.004 Typ. Min. Max. 0.080 0.010 0.070 0.018 - 0.211 0.213 - 0.319 0.031 10 inches
Figure 23. SO8 wide (MW)
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: 1. Drawing is not to scale.
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M25P10
Table 17. Revision History
Date 24-Feb-2000 30-May-2000 Description of Revision Document reformatted in preparation for full release; no parameters changed except data retention, which has been changed to 20 years. Title changed from "Paged Non-Volatile Memory" to "Paged Flash Memory"
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M25P10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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